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Cadence Academic Network

The Cadence Academic Network is a university/industry collaboration to support and to improve Universities activities in the design of analog and digital semiconductors. The INTEC Design group of Ghent University is pleased to join the Cadence Academic Network and to take advantage of the huge benefits this brings to our group through the offering of professional courses, access to new design tools, design support, internships etc.

Training

We leverage Cadence tools to give our Master thesis and PhD students hands-on experience on high-speed mixed-signal or RF IC design. The training of these new IC designers is structured in our lab through a boot camp, which includes intensive hands-on design with Cadence tools, next to the study of essential theory and design methodologies. We have integrated the relevant tutorials and videos of the internet learning series (iLS) and rapid adoption kits (RAKs) provided by Cadence. This eases the learning curve for more advanced tools such as ADE (G)XL and Layout (G)XL. In addition, we use the Generic Process Design Kits as a general introduction to designing in modern process technologies.

Furthermore, we have developed enhancements to Virtuoso to support our work flow or include new functionality. One highlight is the integration of the General Network Theorem as a new analysis.

Research

The IC design activities of our group focus on high-speed and high-frequency front-ends circuits, fiber-optic driver and receiver circuits beyond 40Gb/s such as VCSEL drivers, modulator drivers, transimpedance amplifiers, clock-and-data recovery circuits, and very recently we successfully demonstrated a serial copper interconnect solution beyond 80Gb/s. Our research is not limited to the fundamental research of specific building blocks, but rather focuses on more advanced subsystems for emerging applications thanks to our collaboration with industry and strong involvement in EU funded research. The complexity and challenges associated with advanced (sub-) system design on chip requires the best design tools and training to cope with this complexity during design and verification, on top of the signal and power integrity challenges we often face at high-speed.